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μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Read and Write Cycle
Parameter
Symbol
-E20
Note1
-E22
Note1
-E25
-E30
-E33
Unit
Note
(500 MHz)
(450 MHz)
(400 MHz)
(333 MHz)
(300 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, K#)
TKHKH
2.0
5.25
2.2
5.25
2.5
5.25
3.0
5.25
3.3
5.25
ns
2
Clock phase jitter (K, K#)
Clock HIGH time (K, K#)
Clock LOW time (K, K#)
Clock HIGH to Clock# HIGH
TKC var
TKHKL
TKLKH
TKHK#H
0.4
0.4
0.85
0.15
0.4
0.4
0.95
0.15
0.4
0.4
1.06
0.20
0.4
0.4
1.28
0.20
0.4
0.4
1.40
0.20
ns
TKHKH
TKHKH
ns
3
(K → K#)
Clock# HIGH to Clock HIGH
TK#HKH
0.85
0.95
1.06
1.28
1.40
ns
(K# → K)
DLL/PLL lock time (K)
K static to DLL/PLL reset
TKC lock
TKC reset
20
30
20
30
20
30
20
30
20
30
μ s
ns
4
5
Output Times
CQ HIGH to CQ# HIGH
TCQHCQ#H
0.6
0.7
0.81
1.03
1.15
ns
6
(CQ → CQ#)
CQ# HIGH to CQ HIGH
TCQ#HCQH
0.6
0.7
0.81
1.03
1.15
ns
6
(CQ# → CQ)
K, K# HIGH to output valid
K, K# HIGH to output hold
K, K# HIGH to echo clock valid
K, K# HIGH to echo clock hold
TKHQV
TKHQX
TKHCQV
TKHCQX
– 0.45
– 0.45
0.45
0.45
– 0.45
– 0.45
0.45
0.45
– 0.45
– 0.45
0.45
0.45
– 0.45
– 0.45
0.45
0.45
– 0.45
– 0.45
0.45
0.45
ns
ns
ns
ns
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
K HIGH to output High-Z
K HIGH to output Low-Z
TCQHQV
TCQHQX
TKHQZ
TKHQX1
– 0.15
– 0.45
0.15
0.45
– 0.15
– 0.45
0.15
0.45
– 0.20
– 0.45
0.20
0.45
– 0.20
– 0.45
0.20
0.45
– 0.20
– 0.45
0.20
0.45
ns
ns
ns
ns
7
7
CQ, CQ# HIGH to QVLD valid
Setup Times
TCQHQVLD – 0.15 0.15 – 0.15 0.15 – 0.20 0.20 – 0.20 0.20 – 0.20 0.20
ns
Address valid to K rising edge
Control inputs (R#, W#) valid to
TAVKH
TIVKH
0.33
0.33
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
ns
ns
8
8
K rising edge
Data inputs and write data select
TDVKH
0.25
0.28
0.28
0.28
0.28
ns
8
inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs
TKHAX
TKHIX
0.33
0.33
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
ns
ns
8
8
(R#, W#) hold
K, K# rising edge to data inputs
TKHDX
0.25
0.28
0.28
0.28
0.28
ns
8
and write data select inputs
(BWx#) hold
Notes 1. -E20 and -E22 are valid for 2.5 Clock Cycles Read Latency products.
2. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle regardless of RL = 2.0 and 2.5 clock cycles products in this operation. The AC/DC characteristics
cannot be guaranteed, however.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
18
Data Sheet M19962EJ2V0DS
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